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september 2010 doc id 17546 rev 2 1/27 1 VND830P-E double channel high-side driver features ecopack ? : lead free and rohs compliant automotive grade: compliance with aec guidelines very low standby current cmos compatible input on-state open-load detection off-state open-load detection thermal shutdown protection and diagnosis undervoltage shutdown overvoltage clamp output stuck to v cc detection load current limitation reverse battery protection electrostatic discharge protection description the VND830P-E is a monolithic device made by using stmicroelectronics? vipower? m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the devices against low energy spikes (see iso7637 transient compatibility table). active current limitatio n combined with thermal shutdown and automatic restart protects the device against overload. the device detects open-load condition both is on-state and off-state. output shorted to v cc is detected in the off-state. device automatically turns-off in case of ground pin disconnection. type r ds(on) i out v cc VND830P-E 60 m (1) 1. per each channel. 6a (1) 36 v table 1. device summary package order codes tube tape and reel so-16l VND830P-E vnd830ptr-e www.st.com
VND830P-E contents doc id 17546 rev 2 2/27 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 3.1.1 solution 1: a resistor in the ground line (rgnd only) . . . . . . . . . . . . . . 16 3.1.2 solution 2: a diode (d gnd ) in the ground line . . . . . . . . . . . . . . . . . . . . 17 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 mcu i/o protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 so-16l thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 so-16l package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 so-16l packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VND830P-E list of tables doc id 17546 rev 2 3/27 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6. protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. v cc - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 8. status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 9. switching (v cc = 13 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 10. open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 11. logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 12. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 13. electrical transient requirements on v cc pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 14. electrical transient requirements on v cc pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 15. electrical transient requirements on v cc pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 16. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 17. so-16l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VND830P-E list of figures doc id 17546 rev 2 4/27 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. i lim vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 19. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 20. open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 21. open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 24. open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. so-16l maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 26. so-16l pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 27. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20 figure 28. so-16 l thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 29. thermal fitting model of a quad channel hsd in so-16l . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 30. so-16l package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 31. so-16l tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 32. tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VND830P-E block diagram and pin description doc id 17546 rev 2 5/27 1 block diagram and pin description figure 1. block diagram figure 2. configurati on diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin status n.c. output input floating x x x x to ground - x - through 10 k resistor overtemp. 1 v cc gnd input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 open-load on 1 current limiter 1 open-load off 1 output2 driver 2 clamp 2 open-load on 2 open-load off 2 overtemp. 2 input2 status2 current limiter 2 v cc output 2 output 2 output 2 output 1 v cc output 1 output 1 v cc input 2 status 2 status 1 input 1 v cc gnd n.c. 1 8 9 16
VND830P-E electrical specifications doc id 17546 rev 2 6/27 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in ta b l e 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to th e stmicroelectronics sure progra m and other relevant quality document. table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5 k ; c = 100 pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l = 1.8 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i l = 9 a) 102 mj p tot power dissipation t lead =25c 8.3 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c
VND830P-E electrical specifications doc id 17546 rev 2 7/27 2.2 thermal data 2.3 electrical characteristics values specified in this section are for 8 v < v cc < 36 v; -40 c < t j < 150 c, unless otherwise stated. (per each channel) figure 3. current and voltage conventions 1. v fn = v ccn - v outn during reverse battery condition. table 4. thermal data (per island) symbol parameter value unit r thj-lead thermal resistance junction-lead (max) 15 c/w r thj-amb thermal resistance ju nction-ambient (max) 65 (1) 48 (2) c/w 1. when mounted on a standard single-sided fr-4 board with 0.5 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. 2. when mounted on a standard singl e-sided fr-4 board with 6 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. table 5. power output symbol parameter test conditions min. typ. max. unit v cc (1) operating supply voltage 5.5 13 36 v v usd (1) undervoltage shutdown 3 4 5.5 v v ov (1) overvoltage shutdown 36 v r on on-state resistance i out = 2 a; t j = 25 c i out = 2 a; v cc > 8 v 60 120 m m i s i gnd output 2 v cc gnd status 2 input 2 i out2 i in2 i stat2 v stat2 v in2 v cc v out2 output 1 i out1 v out1 input 1 i in1 status 1 i stat1 v in1 v stat1 v f1 (1)
VND830P-E electrical specifications doc id 17546 rev 2 8/27 i s (1) supply current off-state; v cc = 13 v; v in = v out = 0 v 12 40 a off-state; v cc = 13 v; v in = v out = 0 v; t j = 25c 12 25 a on-state; v cc = 13 v; v in = 5 v; i out = 0 a 57ma i l(off1) off-state output current v in = v out = 0 v 0 50 a i l(off2) off-state output current v in = 0 v; v out = 3.5 v -75 0 a i l(off3) off-state output current v in = v out = 0 v; v cc = 13 v; t j = 125 c 5a i l(off4) off-state output current v in = v out = 0 v; v cc = 13 v; t j =25 c 3a 1. per device. table 6. protections (1) 1. to ensure long term reliability under heavy overload or s hort circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min. typ. max. unit t tsd shutdown temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j > t tsd 20 s i lim current limitation v cc = 13 v 6 9 15 a 5.5 v < v cc < 36 v 15 a v demag turn-off output clamp voltage i out = 2 a; l = 6 mh v cc -41 v cc -48 v cc -55 v table 7. v cc - output diode symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =1.3 a; t j =150c - - 0.6 v table 8. status pin symbol parameter test conditions min. typ. max. unit v stat status low output voltage i stat = 1.6 ma 0.5 v i lstat status leakage current normal operation; v stat = 5 v 10 a c stat status pin input capacitance normal operation; v stat = 5 v 100 pf table 5. power output (continued) symbol parameter test conditions min. typ. max. unit
VND830P-E electrical specifications doc id 17546 rev 2 9/27 v scl status clamp voltage i stat = 1 ma 6 6.8 8 v i stat = - 1 ma -0.7 v table 9. switching (v cc = 13 v) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l = 6.5 from v in rising edge to v out = 1.3 v -30-s t d(off) turn-off delay time r l = 6.5 from v in falling edge to v out = 11.7 v -30-s dv/dt (on) turn-on voltage slope r l = 6.5 from v out = 1.3 v to v out = 10.4 v - see figure 14 -v/s dv/dt (off) turn-off voltage slope r l = 6.5 from v out = 11.7 v to v out = 1.3 v - see figure 15 -v/s table 10. open-load detection symbol parameter test conditions min. typ. max. unit i ol open-load on-state detection threshold v in = 5 v 50 100 200 ma t dol(on) open-load on-state detection delay i out = 0 a 200 s v ol open-load off-state voltage detection threshold v in = 0 v 1.5 2.5 3.5 v t dol(off) open-load detection delay at turn-off 1000 s table 11. logic input symbol parameter test cond itions min. typ. max. unit v il input low level 1.25 v i il low level input current v in = 1.25 v 1 a v ih input high level 3.25 v i ih high level input current v in = 3.25 v 10 a v hyst input hysteresis voltage 0.5 v v icl input clamp voltage i in = 1 ma 6 6.8 8 v i in = -1 ma -0.7 v table 8. status pin (continued) symbol parameter test conditions min. typ. max. unit
VND830P-E electrical specifications doc id 17546 rev 2 10/27 figure 4. switching time waveforms table 12. truth table conditions input output sense normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l
VND830P-E electrical specifications doc id 17546 rev 2 11/27 table 15. electrical transient requirements on v cc pin (part 3) table 13. electrical transient requirements on v cc pin (part 1) iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2ms, 10 2 +25 v +50 v +75 v +100 v 0.2 ms, 10 3a -25 v -50 v -100 v -150 v 0.1 s, 50 3b +25 v +50 v +75 v +100 v 0.1 s, 50 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 5 +26.5v +46.5v +66.5v +86.5v 400ms, 2 table 14. electrical transient requirements on v cc pin (part 2) iso t/r 7637/1 test pulse test levels results i ii iii iv 1 cccc 2 cccc 3a cccc 3b cccc 4 cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
VND830P-E electrical specifications doc id 17546 rev 2 12/27 figure 5. waveforms open-load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc v cc > v ov status input n status n status n input n status n input n open-load with external pull-up undefined overtemperature input n status n t tsd t r t j output voltage n v cc v ol v ol
VND830P-E electrical specifications doc id 17546 rev 2 13/27 2.4 electrical char acteristics curves figure 6. off-state output current figure 7. high level input current figure 8. input clamp voltage figure 9. status leakage current figure 10. status low output voltage figure 11. status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 il(off1) (ua) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.01 0.02 0.03 0.04 0.05 ilstat (ua) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
VND830P-E electrical specifications doc id 17546 rev 2 14/27 figure 12. overvoltage shutdown figure 13. i lim vs t case figure 14. turn-on voltage slope figure 15. turn-off voltage slope figure 16. on-state resistance vs t case figure 17. on-state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 200 250 300 350 400 450 500 550 600 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 20 40 60 80 100 120 140 160 ron (mohm) iout=2a vcc=8v; 13v & 36v 5 10152025303540 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) iout=5a tc= - 40c tc=25c tc=150c
VND830P-E electrical specifications doc id 17546 rev 2 15/27 figure 18. input high level figure 19. input low level figure 20. open-load on-state detection threshold figure 21. open-load off-state detection threshold figure 22. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 70 80 90 100 110 120 130 140 150 iol (ma) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v)
VND830P-E application information doc id 17546 rev 2 16/27 3 application information figure 23. application schematic 3.1 gnd protection network against reverse battery this section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 solution 1: a resistor in the ground line (r gnd only) this can be used with any type of load. the following shows how to dimension the r gnd resistor: 1. r gnd 600 mv / (i s(on)max ) 2. r gnd (-v cc ) / (-i gnd ) where - i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc < 0 during reverse battery situations) is: p d =(-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. v cc output2 d ld +5v r prot output1 status1 input1 +5v status2 input2 gnd +5v c r prot r prot r prot d gnd r gnd v gnd
VND830P-E application information doc id 17546 rev 2 17/27 please note that, if the microprocessor ground is not common with the device ground, then the r gnd produces a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift varies depending on how many devices are on in the case of several high- side drivers sharing the same r gnd . if the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then st suggests using section 3.1.2 described below. 3.1.2 solution 2: a diode (d gnd ) in the ground line a resistor (r gnd =1k ) should be inserted in parallel to d gnd if the device is driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network produce a shift (~600 mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift does not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v cc maximum dc rating. the same applies if the device is subjected to transients on the v cc line that are greater than those shown in ta b l e 1 3 . 3.3 mcu i/o protection if a ground protection network is used and negative transients are present on the v cc line, the control pins are pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the microcontroller i/o pins from latching up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os: -v ccpeak / i latchup r prot (v oh c - v ih - v gnd ) / i ihmax example for the following conditions: v ccpeak = -100 v i latchup 20 ma v oh c 4.5 v 5k r prot 65 k . the recommended values are: r prot = 10 k
VND830P-E application information doc id 17546 rev 2 18/27 3.4 open-load detecti on in off-state off-state open-load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5 v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1. no false open-load indication when load is connected: in this case it needs to avoid v out to be higher than v olmin ; this results in the following condition v out = (v pu / (r l + r pu ))r l < v olmin. 2. no misdetection when load is disconnected: in this case the v out has to be higher than v olmax ; this results in the following condition r pu < (v pu - v olmax ) / i l(off2) . because i s(off) may significantly increase if v out is pulled high (up to several ma), the pull- up resistor r pu should be connected to a supply that is switched off when the module is in standby. the values of v olmin , v olmax and i l(off2) are available in chapter 2: electrical specifications . figure 24. open-load detection in off-state v ol v batt. v pu r pu r l r driver + logic + - in p u t status v cc out ground i l(off2)
VND830P-E application information doc id 17546 rev 2 19/27 3.5 maximum demagn etization energy figure 25. so-16l maximum turn-off current versus load inductance v in , i l t demagnetization demagnetization demagnetization a = single pulse at t jstart = 150 c b= repetitive pulse at t jstart = 100 c c= repetitive pulse at t jstart = 125 c 1 10 100 0,1 1 10 100 l( mh ) i lm ax (a) a b c conditions: v cc = 13.5 v note: values are generated with rl = 0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c.
VND830P-E package and pcb thermal data doc id 17546 rev 2 20/27 4 package and pcb thermal data 4.1 so-16l thermal data figure 26. so-16l pc board (1) figure 27. r thj-amb vs pcb copper area in open box free air condition note: layout condition of r th and z th measurements (pcb fr4 area = 41 mm x 48 mm, pcb thickness = 2 mm, cu thickness = 35 m, copper areas: 0.5 cm 2 , 6 cm 2 ). 40 45 50 55 60 65 70 01234567 pcb cu heatsink area (cm^2) rth j-amb (c/w)
VND830P-E package and pcb thermal data doc id 17546 rev 2 21/27 figure 28. so-16 l thermal impedance junction ambient single pulse equation 1 : pulse calculation formula figure 29. thermal fitting model of a quad channel hsd in so-16l z th r th z thtp 1 ? () + ? = where t p t ? = t_amb pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r2 c1 c2 r1 tj_1 tj_2
VND830P-E package and pcb thermal data doc id 17546 rev 2 22/27 table 16. thermal parameters area/ island (cm 2 ) footprint 6 r1 (c/w) 0.05 r2 (c/w) 0.3 r3 (c/w) 2.2 r4 (c/w) 12 r5 (c/w) 15 r6 (c/w) 37 22 c1 (w.s/c) 0.001 c2 (w.s/c) 5.00e-03 c3 (w.s/c) 0.02 c4 (w.s/c) 0.3 c5 (w.s/c) 1 c6 (w.s/c) 3 5
VND830P-E package and packing information doc id 17546 rev 2 23/27 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 so-16l pac kage information figure 30. so-16l package dimensions
VND830P-E package and packing information doc id 17546 rev 2 24/27 table 17. so-16l mechanical data dim. mm. min. typ. max. a 2.65 a1 0.1 0.2 a2 2.45 b 0.35 0.49 b1 0.23 0.32 c0.5 c1 45 (typ.) d 10.1 10.5 e 10.0 10.65 e1.27 e3 8.89 f7.4 7.6 l 0.5 1.27 m 0.75 s 8 (max.)
VND830P-E package and packing information doc id 17546 rev 2 25/27 5.3 so-16l packing information figure 31. so-16l tube shipment (no suffix) figure 32. tape and reel shipment (suffix ?tr?) base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 a c b base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions
VND830P-E revision history doc id 17546 rev 2 26/27 6 revision history table 18. document revision history date revision changes 25-may-2010 1 initial release. 22-sep-2010 2 changed document status fr om preliminary data to datasheet.
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